1. Field of the Invention
The invention relates to systems and methods for memory organization in an electronic device. More particularly, the invention relates to a system and method for determining optimum resource, e.g., memories and data paths, interconnection patterns in an essentially digital device.
2. Description of the Related Technology
The memory interconnection exploration problem in a customized memory organization context was identified in F. Catthoor et al., ‘Custom Memory Management Methodology’, Kluwer Ac. Publ., 1998, which is hereby incorporated by reference in its entirety.
In an essentially digital device, several resources, such as data paths and memories, are recognized. Such resources may be connected for communication purposes. Such communication allows the execution of the functionality of the digital device. The connections of such resources are referred to as buses in the technology. The quantity of memories within an electronic device, the size of the memories and the interconnection between the memories, including the interconnection of the memories with one or more data paths, defines a memory organization of an electronic device.
Techniques exist to minimize the number of interconnection lines and multiplexers required for connecting the logic gates in data path synthesis. Using these data path synthesis techniques for global memory interconnection implies that the memory interconnection is determined after detailed scheduling. Indeed, the scheduling stage sees the memories as pre-allocated resources which can be accessed in parallel, without taking into account possibilities for time-multiplexing the buses, and may therefore create more conflicts between the data transfers than is strictly necessary to meet the real-time constraints. Further said prior art techniques assume that everything runs at the same clock speed and that all transfers take less than one cycle, which is not the case for memory accessing.
At the level of data path synthesis, no distinction is made between the local buses from register files to functional units, and the global buses between the memories and the data path. There is a huge difference in cost, however, for the global buses. The time-multiplexing overhead is almost negligible compared to the gain of sharing two buses, while in data path synthesis buses are only shared if they have either source or destination in common with each other.
In data path synthesis, the interconnections are situated between sources and destinations. The sources and destinations are known because the full schedule is known. At the global level on the other hand, the data path is treated as a black box, and some of the memories may be multi-ported, so the exact source or destination information for a transfer cannot be known yet. Furthermore, when dealing with a distributed hierarchical background memory organization, memory-to-memory copies are enabled to avoid these copy transfers to be routed via the data path. This makes it practically impossible to assume a source-destination interconnection model for the memory buses.
In the data path context, both buses and multiplexers are equally weighted optimization targets. Moreover, previous approaches do not sufficiently exploit the different bit widths of the signals traveling over the shared bus.
Most of the existing approaches in data transfer binding assume a simple, linear bus structure, but for the global buses there is more freedom. For example, a bus can be split in two by inserting a switch on it. This concept has been utilized already in the technology but the problem regarding the other requirements on memory interconnect addressed herein have not previously been solved.